Milan, Italy

Giuseppe Fornaciari

This inventor holds 1 USPTO granted patent. Top assignee: Lsi Logic Corporation. Active years: 2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Giuseppe Fornaciari. Retrieved from https://idiyas.com/inventor/giuseppe-fornaciari

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 7(Granted Patents)


Company Filing History:


Years Active: 2006

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1 patent (USPTO):Explore Patents

Title: Giuseppe Fornaciari: Innovator in Memory Technology

Introduction

Giuseppe Fornaciari is a notable inventor based in Milan, Italy. He has made significant contributions to the field of memory technology, particularly in the development of advanced testing methods for random access memory.

Latest Patents

Fornaciari holds a patent for a "Method and circuit for scan testing latch based random access memory." This innovative design includes an input data register, an input data buffer coupled to the input data register, a latch array coupled to the input data buffer, and a latch array bypass multiplexer. The multiplexer selects between the input data buffer and the latch array in response to a memory scan mode signal. This allows for the generation of a first data output from the input data buffer during logic scan testing and a second data output from the latch array during memory scan testing. He has 1 patent to his name.

Career Highlights

Giuseppe Fornaciari is currently employed at LSI Logic Corporation, where he continues to work on innovative solutions in memory technology. His expertise in this area has positioned him as a valuable asset to his team and the company.

Collaborations

Fornaciari has collaborated with notable colleagues, including David W. Vinke and Ekambaram Balaji. Their combined efforts have contributed to advancements in the field of memory technology.

Conclusion

Giuseppe Fornaciari's work in memory technology exemplifies the spirit of innovation. His contributions, particularly in scan testing methods, have the potential to enhance the efficiency and reliability of memory systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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