Gerald G Fagerness

Title: Innovations of Gerald G Fagerness

Introduction

Gerald G Fagerness is a notable inventor based in Mazeppa, MN (US). He has made significant contributions to the field of technology, particularly in network processing and hardware design verification. With a total of 6 patents to his name, Fagerness has demonstrated a commitment to advancing innovation.

Latest Patents

One of his latest patents is titled "Methods and apparatus for indexing memory of a network processor." This invention provides a method for address mapping in a network processor, which includes determining a port number, a virtual path identifier, and a virtual channel identifier for a data cell. The method further involves creating an index based on these identifiers and accessing entries in on-chip memory. Another significant patent is "Method and apparatus to verify non-deterministic results in an efficient random manner." This invention focuses on testing and design verification of hardware devices by allowing random accesses to the registers of a device under test, thereby providing a more thorough testing process.

Career Highlights

Throughout his career, Gerald G Fagerness has worked with prominent companies such as Unisys Corporation and International Business Machines Corporation (IBM). His experience in these organizations has contributed to his expertise in the field of technology and innovation.

Collaborations

Fagerness has collaborated with notable individuals in his field, including David C Johnson and Douglas A Fuller. These collaborations have likely enriched his work and contributed to the development of his patents.

Conclusion

Gerald G Fagerness is a distinguished inventor whose work in network processing and hardware design verification has made a lasting impact. His innovative patents and collaborations reflect his dedication to advancing technology.