The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 1999
Filed:
Jan. 23, 1997
Gerald G Fagerness, Mazeppa, MN (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
The present invention relates to a method and apparatus for a greater-than-zero, programmable array fault tolerance used during built-in self-test (BIST) operation. In a first embodiment, a single BIST engine is provided for selected memory elements existing on a die within a logic array. The fault tolerance is set by scanning a register to a number between 0 and 7 to determine the number of faults that are tolerated before the array is considered unusable. After all of the selected memory elements are tested, the die is deemed usable if the total error count does not exceed the fault tolerance contained in the scannable register. Alternatively, each of the selected memory elements on the die may have a dedicated BIST engine. If fault tolerance is enabled for a particular BIST engine, the die will be deemed unusable if more than one fault is detected for the particular memory element associated with the dedicated BIST engine, or alternatively, if the total number of faults detected by all of the BIST engines exceeds the a predetermined fault tolerance number.