This inventor holds 2 USPTO granted patents. Top assignee: Motorola Corporation. Active years: 1996-2000.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 1996-2000
Title: Innovations by Gerald E Vauk, Jr.
Introduction
Gerald E Vauk, Jr. is a notable inventor based in Austin, TX (US). He has made significant contributions to the field of memory access technologies, holding a total of 2 patents. His work primarily focuses on improving the performance of systems that utilize slower memory cores.
Latest Patents
Gerald's latest patents include a method for accessing memory using overlapping accesses. This invention provides a method for synchronously accessing memory to enhance performance in systems with slower cores. The process involves providing a first address during a first clock period and activating control signals to manage the address and data phases of memory access. His other patent, which details a method for synchronously accessing memory, describes how an integrated circuit microprocessor can read data from an external memory device through early overlapping memory access cycles. This innovation allows for efficient access to slower-speed memory, thereby increasing system efficiency.
Career Highlights
Gerald E Vauk, Jr. has had a distinguished career at Motorola Corporation, where he has applied his expertise in memory access technologies. His innovative approaches have contributed to advancements in microprocessor design and memory management.
Collaborations
Throughout his career, Gerald has collaborated with notable colleagues, including Chinh H Le and Terry E Downs. These collaborations have further enriched his work and contributed to the development of cutting-edge technologies in the field.
Conclusion
Gerald E Vauk, Jr. is a prominent inventor whose work in memory access technologies has significantly impacted the efficiency of computing systems. His patents reflect a deep understanding of the challenges posed by slower memory cores and offer innovative solutions to enhance performance.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
