Sunnyvale, CA, United States of America

George F Reyling, Jr

This inventor holds 4 USPTO granted patents. Top assignee: National Semiconductor Corporation. Active years: 1976-1996.

IDiyas Innovation Intelligence. (2026). Inventor Profile: George F Reyling, Jr. Retrieved from https://idiyas.com/inventor/george-f-reyling-jr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 1.5

ph-index = 2

Forward Citations = 83(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (1976 - 1982)
  • Saratoga, CA (US) (1996)

Company Filing History:


Years Active: 1976-1996

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4 patents (USPTO):Explore Patents

Title: Innovations of George F Reyling, Jr.

Introduction

George F Reyling, Jr. is a notable inventor based in Sunnyvale, CA (US). He has made significant contributions to the field of integrated circuits and memory technology. With a total of 4 patents to his name, Reyling has demonstrated a commitment to advancing electronic design and functionality.

Latest Patents

One of Reyling's latest patents is titled "Logical three dimensional interconnections between integrated circuit." This invention describes a high capacity gate array that incorporates an effectively three-dimensional interconnect network. The array is formed from multiple smaller arrays connected to a common substrate through flip-chip bonding. The substrate typically features a multi-layer design with embedded interconnect lines, allowing for desired interconnections between smaller logic cell arrays. The contact points for connecting logic cells to the substrate are achieved by placing solder bumps at specific interconnect points. This innovative approach enables the creation of a three-dimensional interconnect network from a two-dimensional arrangement of arrays, resulting in a high gate capacity logic device with improved operating speed.

Another significant patent by Reyling is "Bubble memory with conductor programmable transparent error map." This invention involves a bubble memory system with multiple data loops, some of which may be defective. The design includes redundant loops and paths for propagating magnetic bubbles. By selectively disabling certain transfer gates associated with defective data loops, Reyling's invention allows for the storage and retrieval of information from redundant loops. This ensures that magnetic bubbles can be merged into the output data stream, enhancing the reliability of the memory system.

Career Highlights

Reyling has worked at National Semiconductor Corporation, where he has contributed to various innovative projects. His work has focused on enhancing the performance and reliability of electronic components, particularly in the realm of integrated circuits and memory technologies.

Collaborations

Throughout his career, Reyling has collaborated with notable colleagues, including Hem P Takiar and James Sutherland. These partnerships have fostered a creative environment that has led to the development of groundbreaking technologies.

Conclusion

George F Reyling, Jr. is a distinguished inventor whose work has significantly impacted the field of electronics. His innovative patents reflect a deep understanding of integrated circuits and memory systems, showcasing his contributions to advancing technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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