Sankt Ruprecht an der Raab, Austria

Georg Parteder

This inventor holds 1 USPTO granted patent. Top assignee: Ams-Osram Ag. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Georg Parteder. Retrieved from https://idiyas.com/inventor/georg-parteder-47thnmms

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Georg Parteder: Semiconductor Through-Substrate Via Innovation.

Introduction

Georg Parteder is an inventor associated with Sankt Ruprecht an der Raab, Austria, and ams-OSRAM AG. His patent work addresses semiconductor-device design and manufacturing, particularly electrical connections that pass through a semiconductor substrate.

Latest Patents

Parteder is credited with 1 patent: “Semiconductor substrate comprising a through-substrate-via and method for producing thereof.” The invention describes a semiconductor device with a substrate, an intermetal dielectric, and a metal layer featuring a top barrier layer. A through-substrate via extends from the substrate’s rear surface through the substrate and dielectric, reaching the barrier layer. Metallization within the via electrically contacts the metal layer from the rear of the substrate.

Career Highlights

The patent reflects work on integrating through-substrate vias with metal layers in semiconductor devices. Such structures provide an electrical connection through the substrate while incorporating the metal layer’s barrier structure into the via’s design.

Collaborations

Parteder’s listed coworkers include Peter Jerabek and Jörg Siegert. The available information identifies these professional associations but does not specify their individual roles in the patent.

Conclusion

Georg Parteder’s recorded patent contribution focuses on a through-substrate-via structure that connects to a metal layer in a semiconductor device, reflecting his association with semiconductor innovation at ams-OSRAM AG.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…