Fort Collins, CO, United States of America

Gary G Kiwimagi

This inventor holds 1 USPTO granted patent. Top assignee: Hewlett-Packard Company. Active years: 2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Gary G Kiwimagi. Retrieved from https://idiyas.com/inventor/gary-g-kiwimagi-epjxsfod

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 17(Granted Patents)


Company Filing History:


Years Active: 2003

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1 patent (USPTO):Explore Patents

Title: Gary G. Kiwimagi: Inventor of a Deadlock-Avoidance System

Introduction

Gary G. Kiwimagi is an inventor associated with Fort Collins, Colorado, and Hewlett-Packard Company. His patent work addresses deadlock prevention in non-preemptive, multithreaded applications.

Latest Patents

Kiwimagi is credited with 1 patent: “System and Method for Avoiding Deadlock in a Non-Preemptive Multi-Threaded Application Running in a Non-Preemptive Multi-Tasking Environment.” The invention places application components that require resources from other components, and do not yield to internal timeslicing, in separate executables. This arrangement is designed to support background processing and avoid deadlock.

Career Highlights

Kiwimagi’s documented patent contribution focuses on coordinating application components in a non-preemptive multitasking environment. The patent identifies a software architecture intended to reduce the risk of components blocking one another while awaiting resources.

Collaborations

Kiwimagi is associated with Hewlett-Packard Company. Ellen M. Nelson is identified as a coworker.

Conclusion

Gary G. Kiwimagi’s patent describes an approach to avoiding deadlock by separating resource-dependent components into distinct executables, reflecting his contribution to software application design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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