Beaverton, OR, United States of America

Gary Foley

This inventor holds 2 USPTO granted patents. Top assignee: Integrated Device Technology, Inc.. Active years: 2004-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Gary Foley. Retrieved from https://idiyas.com/inventor/gary-foley-1vftp6hn

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 2

Forward Citations = 161(Granted Patents)


Company Filing History:


Years Active: 2004-2006

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2 patents (USPTO):Explore Patents

Title: Gary Foley: Innovator in Semiconductor Technology

Introduction

Gary Foley is a notable inventor based in Beaverton, OR (US), recognized for his contributions to semiconductor technology. He holds 2 patents that reflect his innovative approach to solving complex engineering challenges.

Latest Patents

One of Gary Foley's latest patents is titled "Stress-relieved shallow trench isolation (STI) structure and method for forming the same." This invention provides a shallow trench isolation (STI) structure in a semiconductor substrate and outlines a method for its formation. The process involves forming a trench in a semiconductor substrate, where a first dielectric layer is applied to the sidewalls of the trench. This layer is designed to be thicker at the top portion of the sidewalls compared to the bottom, leaving the trench entrance exposed. A second dielectric layer is then conformally formed on the first layer to close the entrance, creating a void buried within the trench. This innovative design significantly reduces stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling.

Career Highlights

Gary Foley is currently employed at Integrated Device Technology, Inc., where he continues to advance semiconductor technologies. His work has been instrumental in developing solutions that enhance the performance and reliability of semiconductor devices.

Collaborations

Throughout his career, Gary has collaborated with esteemed colleagues, including Guo-Qiang (Patrick) Lo and Brian Schorr. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas.

Conclusion

Gary Foley's contributions to semiconductor technology through his patents and collaborations highlight his role as a significant innovator in the field. His work continues to impact the industry positively, paving the way for future advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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