San Jose, CA, United States of America

Gang Yan


Average Co-Inventor Count = 2.1

ph-index = 2

Forward Citations = 11(Granted Patents)


Company Filing History:


Years Active: 2019-2021

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3 patents (USPTO):Explore Patents

Title: Gang Yan: Innovator in Power Supply Circuits and Memory Systems

Introduction

Gang Yan is a prominent inventor based in San Jose, California. He has made significant contributions to the field of electrical engineering, particularly in power supply circuits and memory systems. With a total of three patents to his name, Yan continues to push the boundaries of innovation in technology.

Latest Patents

Gang Yan's latest patents include a phase locked loop-based power supply circuit and method, as well as a chip. The phase locked loop-based power supply circuit is designed to reduce timing variations in digital circuits, facilitating timing closure. This circuit includes a phase locked loop circuit with a voltage-controlled oscillator (VCO) and a voltage regulator, which together provide a stable power supply voltage for load circuits that include logic gates. Additionally, his patent on on-die termination control for memory systems outlines a memory system with multiple memory ranks and local controllers, enhancing the efficiency of memory access and control.

Career Highlights

Gang Yan has established himself as a key figure in his field through his innovative designs and patents. His work at Montage Technology Co., Ltd. has allowed him to collaborate with other talented engineers and contribute to cutting-edge technology solutions.

Collaborations

Some of Gang Yan's notable coworkers include Yibo Jiang and Robert Xi Jin. Their collaborative efforts have further advanced the projects they have worked on together, showcasing the importance of teamwork in innovation.

Conclusion

Gang Yan's contributions to power supply circuits and memory systems exemplify his dedication to innovation in technology. His patents reflect a deep understanding of electrical engineering principles and a commitment to improving digital circuit performance.

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