Ganapathy Parthasarathy

Title: Innovations of Ganapathy Parthasarathy

Introduction

Ganapathy Parthasarathy is an accomplished inventor based in Hillsboro, Oregon. He has made significant contributions to the field of testing methodologies in electronic circuits. His work focuses on improving the reliability and efficiency of built-in self-testing (BIST) techniques.

Latest Patents

Ganapathy holds a patent for a "Method and apparatus for combined stuck-at fault and partial-scanned delay-fault built-in self test." This invention relates to a method and apparatus for combined stuck-fault testing and partial scan delay-fault BIST. The circuit is modeled to break all flip-flop feedback cycles, and a selection of flip-flops is determined from an optimal feedback vertex set. The DDT heuristic can be applied to a weighted signed graph formed from an S-graph of the circuit to determine this optimal feedback vertex set. Additionally, hazards can be removed from the circuit by inserting parity flippers to invert selected paths during testing.

Career Highlights

Ganapathy Parthasarathy has had a notable career, working at Rutgers, The State University of New Jersey. His expertise in circuit testing has positioned him as a valuable asset in the field of electronic engineering. He has collaborated with other professionals to advance testing methodologies.

Collaborations

Ganapathy has worked alongside Michael L. Bushnell, contributing to various projects and research initiatives. Their collaboration has focused on enhancing the effectiveness of testing techniques in electronic circuits.

Conclusion

Ganapathy Parthasarathy's innovative work in circuit testing has led to advancements in built-in self-testing methodologies. His contributions continue to influence the field of electronic engineering and improve the reliability of electronic devices.