Company Filing History:
Years Active: 2019
Title: Inventor Spotlight: Frederico Nascimento-Yoshida
Introduction
Frederico Nascimento-Yoshida, a notable inventor based in San Jose, California, has made significant contributions in the field of electronic circuit design. His innovative approach to formal verification has led to the development of a patented system that enhances the efficiency and accuracy of electronic designs.
Latest Patents
Frederico holds one patent titled "System, method, and computer program product for range-based clock analysis associated with the formal verification of an electronic circuit design." This invention focuses on improving the formal verification process of electronic designs by utilizing various clock configurations. It encompasses a method for receiving an electronic design, identifying a target clock configuration, and selecting clock factor values to perform comprehensive formal verification.
Career Highlights
Currently, Frederico works at Cadence Design Systems, Inc., a leader in electronic design automation (EDA) software. His role involves leveraging cutting-edge technologies to advance electronic design methodologies. With his expertise, Frederico has enhanced the workflow of design verification, ensuring more reliable product outcomes in the technology sector.
Collaborations
Frederico has collaborated closely with his coworker, Matheus Nogueira Fonseca, pooling their expertise to drive forward innovations in electronic design verification. Together, they work on refining approaches that not only streamline design processes but also enhance the overall quality of electronic products.
Conclusion
Frederico Nascimento-Yoshida continues to impact the field of electronic design through his inventive solutions and dedication to formal verification methods. As technology evolves, his contributions are likely to play a pivotal role in shaping the future of electronic design automation and verification.