Sapporo, Japan

Eiichi Sano

This inventor holds 5 USPTO granted patents and 1 EPO patent. Top assignees: Hokkaido University, Semiconductor Technology Academic Research Center, Kyushu Institute of Technology. Active years: 2010-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Eiichi Sano. Retrieved from https://idiyas.com/inventor/eiichi-sano-jfa1demg

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 20.0

 

Average Co-Inventor Count = 2.1

ph-index = 3

Forward Citations = 26(Granted Patents)


Company Filing History:


Years Active: 2010-2014

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5 patents (USPTO):Explore Patents

Title: The Innovations of Eiichi Sano

Introduction

Eiichi Sano is a notable inventor based in Sapporo, Japan. He has made significant contributions to the field of electronics, particularly in the development of advanced circuits and logical devices. With a total of 5 patents to his name, Sano's work reflects a commitment to innovation and technological advancement.

Latest Patents

One of Sano's latest patents is a clock data recovery circuit. This circuit includes a ring oscillator and an oscillation control circuit unit that starts or stops the oscillator based on the presence of a PWM signal. It also features a counter circuit unit that counts pulse signals to hold N bits of count value, along with a register circuit unit that transmits upper M bits of count value as a reference. Additionally, a comparison circuit unit outputs a timing clock when the count value exceeds the reference count value, while a transmission control circuit unit synchronizes with the PWM signal to generate necessary signals for operation.

Another significant patent is the complementary logic gate device. This device is represented by a silicon CMOS logical circuit among semiconductor integrated logical circuits. It effectively addresses the speed performance limits of ultra-large scale integration and ultra-low power consumption. The device includes an electron running layer formed by graphene, utilizing only two FETs with different threshold values. This innovative design allows for improved performance in logical circuits.

Career Highlights

Eiichi Sano has worked with prestigious institutions such as Hokkaido University and the Semiconductor Technology Academic Research Center. His experience in these organizations has contributed to his expertise in semiconductor technology and circuit design.

Collaborations

Sano has collaborated with notable individuals in his field, including Taiichi Otsuji and Masato Koutani. These collaborations have likely enriched his work and led to further advancements in technology.

Conclusion

Eiichi Sano's contributions to the field of electronics through his innovative patents and collaborations highlight his role as a significant inventor. His work continues to influence advancements in circuit design and semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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