Pleasanton, CA, United States of America

Edward Wayne Pesuit

This inventor holds 1 USPTO granted patent. Top assignee: Siemens Business Communication Systems, Inc.. Active years: 1998.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Edward Wayne Pesuit. Retrieved from https://idiyas.com/inventor/edward-wayne-pesuit

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 1.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 1998

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1 patent (USPTO):Explore Patents

Title: Edward Wayne Pesuit: Innovator in Memory Addressing Technology.

Introduction

Edward Wayne Pesuit is a notable inventor based in Pleasanton, CA (US). He has made significant contributions to the field of memory addressing technology. His innovative approach has led to the development of a unique patent that enhances the capabilities of microprocessors.

Latest Patents

Edward Wayne Pesuit holds a patent for "Multiple memory addressing using adjustable chip select." This invention allows for the overlaying of two memory banks to form a single, monolithic memory. By setting a movable boundary point between these two banks, it is possible to exceed the fixed addressing capability of a microprocessor. The manipulation of this boundary can be performed by a microprocessor, enabling access to common-value memory locations in either of the memory regions.

Career Highlights

Edward Wayne Pesuit is associated with Siemens Business Communication Systems, Inc. His work at this company has allowed him to apply his innovative ideas in a practical setting, contributing to advancements in communication technology.

Collaborations

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Conclusion

Edward Wayne Pesuit's contributions to memory addressing technology exemplify the impact of innovation in the field of microprocessors. His patent demonstrates a significant advancement that can enhance the performance of memory systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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