Cambridge, MA, United States of America

Douglas La Tulipe

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: The Charles Stark Draper Laboratory, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Douglas La Tulipe. Retrieved from https://idiyas.com/inventor/douglas-la-tulipe-8yte8wou

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Douglas La Tulipe and Dynamic Security Fabric Interposers

Introduction

Douglas La Tulipe is an inventor associated with The Charles Stark Draper Laboratory, Inc., in Cambridge, Massachusetts. His patent work addresses security features for heterogeneously integrated semiconductor systems.

Latest Patents

La Tulipe is named on 1 patent: “Systems and Methods for Providing Dynamic Security Fabric Interposers in Heterogeneously Integrated Systems.” The patent describes an integrated-circuit package containing one or more dies connected to an interposer through an interconnection layer. Electrically active devices in the interposer can provide security functions for circuits on the dies. The design may also connect the interposer to the package’s backside power system, which can include backside power-delivery networks.

Career Highlights

The available information identifies La Tulipe as an inventor working with The Charles Stark Draper Laboratory, Inc. His patent reflects work on integrating security functions into semiconductor packaging, including interposers and backside power architectures.

Collaborations

The patent lists La Tulipe’s association with The Charles Stark Draper Laboratory, Inc. The supplied information does not identify additional collaborators.

Conclusion

Douglas La Tulipe’s patent focuses on using electrically active interposers to add security functions to heterogeneously integrated systems, connecting semiconductor packaging design with circuit protection.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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