Hwaseong-si, South Korea

Doo Hyun Lee

This inventor holds 2 USPTO granted patents. Top assignee: Samsung Electronics Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Doo Hyun Lee. Retrieved from https://idiyas.com/inventor/doo-hyun-lee-26yixbug

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.8

ph-index = 1


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Doo Hyun Lee: Semiconductor Device Inventor

Introduction

Doo Hyun Lee is an inventor based in Hwaseong-si, South Korea, whose patent work focuses on semiconductor device structures and fabrication. He works at Samsung Electronics. His portfolio includes 2 patents.

Latest Patents

Lee’s recent patent work includes two inventions related to semiconductor devices.

“Nanosheet Semiconductor Device Having a Through Via Extending Through a Source/Drain Region Between Two Active Region Separation Cuts” describes a device with multiple active patterns and separation cuts. A vertical through via passes through an active pattern between two cuts and extends into the substrate.

“Semiconductor Device Including Source/Drain Pattern Having High Concentration Impurity Region and Method for Fabricating the Same” concerns a source/drain structure and its contact. The design includes silicon-germanium liner, filling, and insertion films, along with a contact silicide film positioned between the contact and source/drain region.

Career Highlights

Lee’s listed patents address nanosheet device architecture, through-via integration, and source/drain contact structures. These inventions reflect work on semiconductor design and fabrication at Samsung Electronics.

Collaborations

Lee’s listed coworkers include Jin Young Park and Heon Jong Shin.

Conclusion

Doo Hyun Lee’s patent portfolio highlights his contributions to semiconductor device engineering, particularly nanosheet structures and source/drain technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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