Taejon, South Korea

Dong Soo Han

This inventor holds 1 USPTO granted patent. Top assignee: Electronics and Telecommunications Research Institute. Active years: 2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dong Soo Han. Retrieved from https://idiyas.com/inventor/dong-soo-han-2h9dyhpb

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 12(Granted Patents)


Company Filing History:


Years Active: 2006

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1 patent (USPTO):Explore Patents

Title: Innovations of Dong Soo Han in Parallel Programming

Introduction

Dong Soo Han is a notable inventor based in Taejon, South Korea. He has made significant contributions to the field of parallel programming, particularly in race detection methods. His work is essential for improving the reliability and efficiency of parallel programs.

Latest Patents

Dong Soo Han holds a patent titled "Parallel loop transformation methods for race detection during an execution of parallel programs." This innovative method involves generating a data structure of a condition statement branch determinant string, which is crucial for loop transformation. The process includes transforming the original parallel loop into a full race covering loop and instrumenting the race detection function to ensure accurate detection during the execution of parallel programs.

Career Highlights

Dong Soo Han is affiliated with the Electronics and Telecommunications Research Institute, where he continues to advance research in parallel programming. His expertise in race detection has positioned him as a key figure in this area of study.

Collaborations

He has collaborated with notable colleagues, including Jeong Si Kim and Chan Su Yu, contributing to various projects that enhance the understanding and application of parallel programming techniques.

Conclusion

Dong Soo Han's innovative work in parallel programming and race detection methods showcases his commitment to advancing technology in this critical field. His contributions are invaluable for the future of parallel computing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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