Yongin-si, South Korea

Dong Hyun Won

This inventor holds 2 USPTO granted patents. Top assignee: Samsung Display Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dong Hyun Won. Retrieved from https://idiyas.com/inventor/dong-hyun-won-7ed13h5f

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.0


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Dong Hyun Won: Display Technology Inventor

Introduction

Dong Hyun Won is an inventor based in Yongin-si, South Korea. His patent work focuses on display-device structures and semiconductor components used in display technology. He is associated with Samsung Display Co., Ltd. and is named on 2 patents.

Latest Patents

Won’s listed patents address display-device design and manufacturing.

- **Display device.** This invention describes a substrate with a light-emitting element on one surface and its driving unit on the opposite surface. Side wiring connects pads on the two surfaces, with separate wiring paths extending across the substrate’s side surface.

- **Display device with active layer opening parts and method of manufacturing the same.** This invention describes a semiconductor layer with multiple parts and openings, together with gate and connecting electrodes. The connecting-electrode geometry is designed to connect directly to semiconductor regions and extend toward the openings.

Career Highlights

Won’s listed inventions reflect work on electrical connections across display substrates and on the structure of semiconductor layers and electrodes. Both patents concern components that support the operation and manufacture of display devices.

Collaborations

Won’s listed coworkers include Yong Duck Son and Yoon Ho Lee. His company affiliation is Samsung Display Co., Ltd.

Conclusion

Dong Hyun Won’s patent portfolio highlights contributions to display-device engineering, particularly substrate wiring and semiconductor-layer design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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