This inventor holds 1 USPTO granted patent. Top assignee: Via Technologies, Inc.. Active years: 2007.
Company Filing History:
Years Active: 2007
Title: Derek Edward Davout Gladding: Innovator in Processor Technology
Introduction
Derek Edward Davout Gladding is a notable inventor based in San Francisco, CA. He has made significant contributions to the field of processor technology, particularly in enhancing register addressing space in instruction-width limited processors. His innovative approach has the potential to improve the efficiency of instruction execution in modern computing systems.
Latest Patents
Derek holds a patent for "Systems for increasing register addressing space in instruction-width limited processors." This patent presents a system for executing instructions that includes functional units, local multiplexers, local register files, and a global register file. These components are designed to work together to accommodate shortened instruction words in multiple-issue processors. By allowing greater access to registers by instructions, this system enables a reduction in word length compared to conventional very long instruction word (VLIW) processors.
Career Highlights
Derek is currently employed at Via Technologies, Inc., where he continues to develop innovative solutions in processor technology. His work focuses on improving the efficiency and performance of computing systems through advanced architectural designs.
Collaborations
Derek has collaborated with several talented individuals in his field, including Boris Prokopenko and Timour T Paltashev. These collaborations have contributed to the advancement of technology and innovation in processor design.
Conclusion
Derek Edward Davout Gladding is a prominent inventor whose work in processor technology has the potential to reshape the landscape of computing. His patent and contributions to Via Technologies, Inc. highlight his commitment to innovation and excellence in the field.