Shelburne, VT, United States of America

Dave Eugene Chapmen


Average Co-Inventor Count = 3.8

ph-index = 2

Forward Citations = 12(Granted Patents)


Company Filing History:


Years Active: 2009-2012

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7 patents (USPTO):

Title: The Innovations of Dave Eugene Chapmen

Introduction

Dave Eugene Chapmen is a notable inventor based in Shelburne, Vermont. He has made significant contributions to the field of technology, particularly in chip design and operational frequency detection. With a total of 7 patents to his name, Chapmen continues to push the boundaries of innovation.

Latest Patents

Chapmen's latest patents include a groundbreaking chip system designed to reduce power consumption under specific operational modes. This DDR3 chip features a plurality of pads located at its center, surrounded by an array of banks, each with a specific logical address. The system also incorporates a clock for controlling data transmission rates and a memory controller for coordinating data processes and reassigning bank logical addresses based on operational modes. Another significant patent involves a method for detecting minimum operational frequency. This method generates an oscillating signal at a predetermined frequency and produces a logic signal that transitions when the frequency reaches a second predetermined level, indicating the minimum operational frequency.

Career Highlights

Chapmen is currently employed at Nan Ya Technology Corporation, where he applies his expertise in chip technology and frequency detection. His work has been instrumental in advancing the capabilities of modern electronic devices.

Collaborations

Some of his notable coworkers include Ryan Andrew Jurasek and Bret Roberts Dale, who have collaborated with him on various projects within the technology sector.

Conclusion

Dave Eugene Chapmen's contributions to technology through his innovative patents and work at Nan Ya Technology Corporation highlight his role as a leading inventor in the field. His ongoing efforts continue to shape the future of chip design and operational efficiency.

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