The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2012

Filed:

Oct. 12, 2009
Applicants:

Richard Michael Parent, Shelburne, VT (US);

Ryan Andrew Jurasek, S. Burlington, VT (US);

Dave Eugene Chapmen, Shelburne, VT (US);

Inventors:

Richard Michael Parent, Shelburne, VT (US);

Ryan Andrew Jurasek, S. Burlington, VT (US);

Dave Eugene Chapmen, Shelburne, VT (US);

Assignee:

Nanya Technology Corp., Kueishan, Tao-Yuan Hsien, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/00 (2006.01); G11C 8/00 (2006.01); G06F 11/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.


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