Taejon, South Korea

Dae Seon Park

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignee: Electronics and Telecommunications Research Institute. Active years: 2010-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dae Seon Park. Retrieved from https://idiyas.com/inventor/dae-seon-park-ty1s1lqt

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

% Patents Active = 50.0

Average Co-Inventor Count = 4.0

ph-index = 1


Location History:

  • Taejon, KR (2010)
  • Daejeon, KR (2017)

Company Filing History:


Years Active: 2010-2017

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2 patents (USPTO):Explore Patents

Title: Dae Seon Park: Innovator in Memory Data Erasure Technologies

Introduction

Dae Seon Park is a notable inventor based in Taejon, South Korea. He has made significant contributions to the field of memory data erasure technologies, holding 2 patents that showcase his innovative approach to data security.

Latest Patents

One of his latest patents is titled "Method and apparatus for erasing memory data." This invention focuses on a memory erasing method and apparatus designed to erase important data from a nonvolatile memory. It utilizes attitude information measured by an inertial measurement sensor and a low power microprocessor to prevent illegal access, regardless of the power supply state of the apparatus. The apparatus features a power switching circuit that selects between an external power source and a battery. The inertial measurement sensor measures the apparatus's attitude information, while the low power microprocessor erases important data in two distinct manners, depending on the power source used.

Another significant patent by Dae Seon Park is the "Shrinking key generator for parallel process." This invention provides a parallel processing shrinking key generator that includes a selection linear feedback shift register (LFSR) and a source LFSR. It also features a selection logic circuit that chooses between a source bit from the source LFSR and a predetermined input bit based on a selection bit from the selection LFSR. An index counter assigns an index for storing output bits, and an output amount register shifts the output bit according to the index counter's assignment.

Career Highlights

Dae Seon Park is affiliated with the Electronics and Telecommunications Research Institute, where he continues to develop innovative technologies. His work has significantly impacted the field of data security and memory management.

Collaborations

He has collaborated with notable coworkers, including Jung Hyung Park and Jang Hong Yoon, contributing to various projects and advancements in technology.

Conclusion

Dae Seon Park's contributions to memory data erasure technologies highlight his innovative spirit and dedication to enhancing data security. His patents reflect a deep understanding of the challenges in the field and offer practical solutions to address them.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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