Chapareillan, France

Cleonisse Serrecchia

This inventor holds 1 USPTO granted patent and 1 EPO patent. Top assignee: Altatech Semiconductor. Active years: 2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Cleonisse Serrecchia. Retrieved from https://idiyas.com/inventor/cleonisse-serrecchia

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

 

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2015

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1 patent (USPTO):Explore Patents

Title: Cleonisse Serrecchia: Innovator in Semiconductor Wafer Inspection

Introduction

Cleonisse Serrecchia is a notable inventor based in Chapareillan, France. He has made significant contributions to the field of semiconductor technology, particularly in the area of wafer inspection. His innovative approach has led to the development of a unique device that enhances the efficiency and accuracy of semiconductor wafer inspections.

Latest Patents

Cleonisse Serrecchia holds 1 patent for his invention titled "Device and method for inspecting semiconductor wafers." This semiconductor wafer inspection device features a wafer transport arm equipped with at least one wafer support element and a wafer gripper. The gripper is designed with two distant branches that securely hold the opposed edges of the wafer. It is mounted to rotate on a shaft, allowing the wafer to transition between an approximately horizontal position and an approximately vertical position. Additionally, the device includes at least two inspection systems positioned symmetrically on either side of the wafer, enhancing the inspection process.

Career Highlights

Throughout his career, Cleonisse Serrecchia has worked with prominent companies in the semiconductor industry. Notably, he has been associated with Altatech Semiconductor and Unity Semiconductor Corporation. His experience in these organizations has contributed to his expertise in semiconductor technologies and innovations.

Collaborations

Cleonisse has collaborated with several professionals in his field, including Philippe Gastaldo and François Berger. These collaborations have likely enriched his work and contributed to the advancements in semiconductor wafer inspection technologies.

Conclusion

Cleonisse Serrecchia's contributions to semiconductor wafer inspection demonstrate his innovative spirit and technical expertise. His patented device represents a significant advancement in the industry, showcasing his commitment to improving semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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