Santa Clara, CA, United States of America

Chunya Wen

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Alpha and Omega Semiconductor International LP. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chunya Wen. Retrieved from https://idiyas.com/inventor/chunya-wen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chunya Wen and Semiconductor Packaging Innovation.

Introduction

Chunya Wen is an inventor based in Santa Clara, California. His work includes semiconductor packaging, with a patent describing a package that integrates multiple chips and redistribution layers.

Latest Patents

Wen is associated with 1 patent: “Semiconductor Package Having Multiple Redistribution Layers and Method of Making the Same.” The invention describes a semiconductor package containing two or more chips, multiple molding layers, and bottom, middle, and top redistribution layers. Its top redistribution layer includes two copper plates, with vias electrically connecting one plate to the second chip.

The disclosed manufacturing method forms the chip-level molding layer and middle redistribution layer, followed by additional molding layers and the bottom and top redistribution layers. These components are assembled to fabricate the semiconductor package.

Career Highlights

Wen is associated with Alpha and Omega Semiconductor International LP. His patent focuses on a layered packaging architecture and a process for manufacturing it.

Collaborations

The provided information identifies Zhiqiang Niu and Rhys Philbrick as Wen’s coworkers. It does not specify their roles in the patent or whether they collaborated on the invention.

Conclusion

Chunya Wen’s patent documents an approach to semiconductor packaging that combines multiple chips, redistribution layers, and molding layers in a structured manufacturing process.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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