Taipei, Taiwan

Chung-hsin Lin

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignee: Nan Ya Technology Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chung-hsin Lin. Retrieved from https://idiyas.com/inventor/chung-hsin-lin-koffqoab

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Chung-hsin Lin: Innovator in Semiconductor Technology

Introduction

Chung-hsin Lin is an inventor based in Taipei, Taiwan. He is recognized for his contributions to the field of semiconductor technology. Although he currently holds no granted patents, his work in developing innovative methods for semiconductor devices is noteworthy.

Latest Patent Applications

Chung-hsin Lin has filed several patent applications, including a significant one titled "METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING 3D MEMORY STRUCTURE." This application describes a semiconductor device that comprises a substrate, a word line, a first capacitor, a second capacitor, a first bit line, and a second bit line. The word line is positioned on the substrate and extends in a specific direction. The first capacitor is oriented in a different direction and is situated at a first level, while the second capacitor is at a different level. The first bit line connects electrically to the first capacitor and the word line, and the second bit line connects to the second capacitor and the word line.

Conclusion

Chung-hsin Lin's innovative approaches in semiconductor technology highlight his potential impact in the field, despite not yet having granted patents. His latest patent applications reflect a commitment to advancing semiconductor device manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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