Austin, TX, United States of America

Chris J Micielli

This inventor holds 1 USPTO granted patent. Top assignee: Freescale Semiconductor,inc.. Active years: 2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chris J Micielli. Retrieved from https://idiyas.com/inventor/chris-j-micielli

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2016

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1 patent (USPTO):Explore Patents

Title: Chris J. Micielli and His Patent for LVDS with an Idle State.

Introduction

Chris J. Micielli is an inventor associated with Austin, Texas, and Freescale Semiconductor, Inc. His listed patent concerns low-voltage differential signaling (LVDS), a technology used to transmit signals through differences in voltage between two output nodes.

Latest Patents

Micielli is credited with 1 patent: “LVDS with Idle State.” The patent describes a signal-generating circuit with a current source, two output nodes, differential switch circuits, and bypass circuitry. The switch circuits direct current between the output nodes according to a control signal. During idle mode, the bypass circuitry is switched to prevent current from flowing between the nodes.

Career Highlights

Micielli’s listed work at Freescale Semiconductor, Inc. connects his inventive contribution to the development of electronic signaling circuitry. His patent focuses on controlling current flow during active signaling and reducing it in the idle state.

Collaborations

The provided information names Jonathan M. Phillippe and Gilford E. Lubbers as Micielli’s coworkers. Their inclusion indicates professional associations, but no specific joint patent work is described in the supplied details.

Conclusion

Chris J. Micielli’s listed patent addresses an LVDS circuit designed to manage differential signaling and prevent current flow between output nodes during idle mode.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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