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Bayan Lepas, Malaysia

Choi Phaik Chin

This inventor holds 5 USPTO granted patents. Top assignee: Altera Corporation. Active years: 2013-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Choi Phaik Chin. Retrieved from https://idiyas.com/inventor/choi-phaik-chin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5

% Patents Active = 60.0

Average Co-Inventor Count = 2.3

ph-index = 2

Forward Citations = 16(Granted Patents)

Location History:

Penang, MY (2013 - 2014)
Gelugor, MY (2014)
Bayan Lepas, MY (2014 - 2019)

Company Filing History:

Altera Corporation

Years Active: 2013-2019

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5 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10331843 - System and method for visualization and analysis of a chip view including multiple circuit design revisions (2019-06-25),

2. 8924913 - Schematic display of connectivity in an integrated circuit design (2014-12-30),

3. 8898618 - Interactive simplification of schematic diagram of integrated circuit design (2014-11-25),

4. 8788997 - Method for simplifying RTL schematic by grouping nodes into a cloud (2014-07-22),

5. 8495546 - Method for simplifying RTL schematic by grouping nodes into a cloud (2013-07-23),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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