Hsinchu, Taiwan

Ching-Lun Lai

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ching-Lun Lai. Retrieved from https://idiyas.com/inventor/ching-lun-lai-6zep62tu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Ching-Lun Lai and FinFET Innovation

Introduction

Ching-Lun Lai is an inventor associated with Hsinchu, Taiwan, and Taiwan Semiconductor Manufacturing Co., Ltd. Her work includes a patented process for controlling dopants in a FinFET transistor.

Latest Patents

The provided information lists one patent for Lai: “Integrated Circuit with Anti-Punch Through Control.” The invention describes a FinFET transistor with an anti-punch-through region beneath its channel. During fabrication, a dielectric layer is placed in the source and drain recesses, and annealing allows undesirable dopants to diffuse from the anti-punch-through region into that layer. The dielectric is then removed, and semiconductor material is deposited to form the source and drain regions. This process helps control dopants in the transistor structure. Lai is credited with 1 patent in the supplied data.

Career Highlights

Lai’s listed patent concerns semiconductor device fabrication and FinFET design. The supplied information associates her with Taiwan Semiconductor Manufacturing Co., Ltd., a semiconductor company based in Taiwan.

Collaborations

The provided data names Yi-Chen Ho and Chien Lin as Lai’s coworkers. It does not specify their roles in the patent or describe particular collaborative contributions.

Conclusion

Ching-Lun Lai’s listed invention addresses dopant control during FinFET fabrication, reflecting a focused contribution to semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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