Santa Clara, CA, United States of America

Chiente Ho

USPTO Granted Patents = 2 

 

Average Co-Inventor Count = 3.7

ph-index = 2

Forward Citations = 7(Granted Patents)


Company Filing History:


Years Active: 2006-2017

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2 patents (USPTO):Explore Patents

Title: Chiente Ho: Innovator in Processor Emulation and 3D Graphics

Introduction

Chiente Ho is a notable inventor based in Santa Clara, CA. He has made significant contributions to the fields of processor emulation and 3D graphics. With a total of 2 patents, his work has had a lasting impact on technology.

Latest Patents

Chiente Ho's latest patents include "Emulation of Fused Multiply-Add Operations" and "Vertex Reordering in 3D Graphics." The first patent describes a method where at least one processor emulates a fused multiply-add operation involving three operands. This process includes determining intermediate values and rounding them to achieve accurate results. The second patent outlines a method for reordering the vertices of a graphics primitive. It involves receiving vertices in a circular order and using comparison logic to identify the minimum vertex, ensuring that the vertices are shuffled into the correct order for optimal graphics rendering.

Career Highlights

Throughout his career, Chiente Ho has worked with prominent companies such as Via Technologies, Inc. and Qualcomm Incorporated. His experience in these organizations has allowed him to develop innovative solutions that enhance processing capabilities and graphics performance.

Collaborations

Chiente Ho has collaborated with talented individuals in the industry, including Hsilin Huang and Jeff Jiao. These partnerships have contributed to the advancement of his projects and the successful implementation of his inventions.

Conclusion

Chiente Ho's contributions to processor emulation and 3D graphics exemplify his innovative spirit and technical expertise. His patents reflect a commitment to enhancing technology and improving user experiences in computing and graphics.

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