This inventor holds 1 USPTO granted patent. Top assignee: National Science Council. Active years: 2002.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2002
Title: Innovations of Chien-Hsing Lin in Semiconductor Technology.
Introduction
Chien-Hsing Lin is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor technology, particularly in the area of interconnection processes. His work has implications for improving the efficiency and reliability of electronic devices.
Latest Patents
Chien-Hsing Lin holds 1 patent for his invention titled "Process for preparing Cu damascene interconnection." This patent discloses a technique aimed at enhancing adhesion between a passivation layer and a low-K dielectric layer. The method involves subjecting a SiO layer, formed as the passivation on the low-K dielectric layer, to N2O plasma annealing. This innovative technique is beneficial in improving the yield of processes for preparing Cu damascene interconnections.
Career Highlights
Chien-Hsing Lin is associated with the National Science Council, where he has been involved in advanced research and development projects. His expertise in semiconductor processes has positioned him as a valuable asset in the field.
Collaborations
Chien-Hsing Lin has collaborated with notable colleagues, including Ching-Fa Yeh and Yueh-Chuan Lee. Their combined efforts have contributed to advancements in semiconductor technologies.
Conclusion
Chien-Hsing Lin's innovative work in semiconductor technology, particularly his patented process for Cu damascene interconnection, showcases his commitment to enhancing electronic device performance. His contributions continue to influence the industry positively.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile