Chia-Ming Ho

Title: Innovations by Chia-Ming Ho in VLSI Power Consumption

Introduction

Chia-Ming Ho is a notable inventor based in Tao-Yuan, Taiwan. He has made significant contributions to the field of Very Large Scale Integration (VLSI) design, particularly in methods aimed at reducing power consumption in electronic circuits. His innovative approach has garnered attention in the engineering community.

Latest Patents

Chia-Ming Ho holds a patent for a method on scan chain reordering for lowering VLSI power consumption. This method focuses on reordering a scan chain to meet specific constraints while minimizing peak power dissipation. The constraints include a maximum peak power dissipation, a maximum scan chain length, and a maximum distance between two successive registers. The method integrates a developed tool into an existing VLSI design flow, facilitating low-power circuit designs. Additionally, it features characteristics that quickly assess whether feasible solutions exist and aids in searching for the optimal solution. The modified data derived from the scan chain declaration and scan pattern data adheres to the established constraints.

Career Highlights

Chia-Ming Ho is affiliated with Chang Gung University, where he continues to advance research in VLSI design and power efficiency. His work has been instrumental in developing methodologies that enhance the performance and sustainability of electronic devices.

Collaborations

Chia-Ming Ho has collaborated with notable colleagues, including Herng-Jer Lee and Chia-Chi Chu. Their joint efforts contribute to the ongoing research and development in the field of VLSI technology.

Conclusion

Chia-Ming Ho's innovative methods in VLSI power consumption represent a significant advancement in electronic design. His contributions not only enhance circuit efficiency but also pave the way for future innovations in low-power technologies.