Hsinchu, Taiwan

Chia-Hsuan Wang

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chia-Hsuan Wang. Retrieved from https://idiyas.com/inventor/chia-hsuan-wang-2w9xm4eo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chia-Hsuan Wang and Semiconductor Device Innovation.

Introduction

Chia-Hsuan Wang is an inventor associated with Hsinchu, Taiwan, and Taiwan Semiconductor Manufacturing Co., Ltd. The supplied information identifies her as a woman and credits her with 1 patent.

Latest Patents

Wang’s listed patent is “Method of Forming a Nano-FET Semiconductor Device.” The invention describes nanostructure devices and methods for making them, including a treatment process that expands sidewall spacer material to close a seam after deposition. Oxygen plasma treatment expands the material and crosslinks the open seam, producing a closed seam while lowering the material’s k-value and decreasing its density.

Career Highlights

Wang’s listed patent focuses on fabrication techniques for nano-FET semiconductor devices. The approach addresses seam formation in sidewall spacers, a feature relevant to the construction of nanostructure devices.

Collaborations

The supplied information lists Li-Chi Yu and Cheng-I Chu as Wang’s coworkers. Their names are provided as professional associations, though specific roles in the patent are not stated.

Conclusion

Chia-Hsuan Wang’s listed work reflects an innovation in semiconductor device fabrication, using oxygen plasma treatment to improve sidewall spacer formation in nano-FET structures.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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