Hsinchu, Taiwan

Chia-Hsi Wang

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chia-Hsi Wang. Retrieved from https://idiyas.com/inventor/chia-hsi-wang-bz6krsws

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chia-Hsi Wang: Inventor in Semiconductor Deposition Technology.

Introduction

Chia-Hsi Wang is an inventor based in Hsinchu, Taiwan, associated with Taiwan Semiconductor Manufacturing Co., Ltd. Her work includes an invention focused on improving the reliability and operating time of deposition systems used in semiconductor processing.

Latest Patents

Wang is named on one patent, 1 patent: “Deposition System and Method.” The invention describes a system designed to reduce thermal-stress deformation of a target and other components during sputtering. It uses a substrate process chamber, a target, and circularly arranged grooves on the target, including grooves at its center and periphery. By helping maintain the temperature within a predetermined range, the design aims to extend the chamber’s operating time.

Career Highlights

Wang’s listed patent work concerns semiconductor manufacturing equipment and addresses thermal management during deposition. The disclosed approach uses target geometry to help limit deformation caused by heat generated in the sputtering process.

Collaborations

The available information associates Wang’s invention with Taiwan Semiconductor Manufacturing Co., Ltd. It does not specify additional collaborators or describe the details of her role at the company.

Conclusion

Chia-Hsi Wang’s patent describes a practical approach to managing thermal stress in deposition equipment, with the goal of supporting longer chamber operation in semiconductor manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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