Hsinchu, Taiwan

Cheng-Chien Li

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Cheng-Chien Li. Retrieved from https://idiyas.com/inventor/cheng-chien-li-80xp287i

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Cheng-Chien Li: Semiconductor Invention and Patent

Introduction

Cheng-Chien Li is an inventor associated with Hsinchu, Taiwan, and Taiwan Semiconductor Manufacturing Co., Ltd. His patent work concerns semiconductor device structures and manufacturing methods.

Latest Patents

The available information lists 1 patent for Li: “Devices with Through Silicon Vias, Guard Rings and Methods of Making the Same.” The invention describes a semiconductor article with a semiconductor substrate, a back-end-of-line (BEOL) wiring portion, a through-silicon via, and a guard ring. The via provides a conductive path through the BEOL wiring and substrate, while the guard ring surrounds the via in the BEOL portion and, in some embodiments, also in the substrate. The BEOL portion contains multiple wiring layers made up of conductive wiring and insulating material.

Career Highlights

Li’s listed patent reflects work on integrating through-silicon vias and guard rings into semiconductor structures. These features are relevant to the design and fabrication of devices that route electrical connections through a semiconductor substrate.

Collaborations

Min-Feng Ku and Yao-Chun Chuang are identified as Li’s coworkers. The available information does not specify their roles in the patent or whether they collaborated directly on the invention.

Conclusion

Cheng-Chien Li’s listed patent documents an invention combining through-silicon vias and guard rings, highlighting his contribution to semiconductor device technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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