Cheisen J Yue

Title: Cheisen J Yue: Innovator in CMOS SOI Technology

Introduction

Cheisen J Yue is a notable inventor based in Roseville, MN (US). He has made significant contributions to the field of semiconductor technology, particularly in the development of methods for integrated circuits. His innovative approach has led to the creation of a patent that enhances the performance of CMOS SOI devices.

Latest Patents

Cheisen J Yue holds a patent for "Recessed silicon oxidation for devices such as a CMOS SOI ICs." This patent describes a method to form LOCOS isolation in a CMOS SOI device. The process involves a top silicon layer, a bottom silicon layer, and an insulation layer between them. An oxide layer is formed over the top silicon layer, followed by the deposition of an LPCVD layer. A photoresist is applied to expose a localized area of the LPCVD layer, allowing for the etching away of both the LPCVD and oxide layers to reveal the top silicon layer. The silicon in this layer is then etched to create a recess, and an isolation oxide is grown to fully oxidize the silicon in the recess.

Career Highlights

Cheisen J Yue is currently employed at Honeywell International Inc., where he continues to work on innovative technologies in the semiconductor industry. His expertise and dedication to research have positioned him as a valuable asset to his team.

Collaborations

One of his notable coworkers is Eric E Vogt, with whom he collaborates on various projects within the company.

Conclusion

Cheisen J Yue's contributions to CMOS SOI technology exemplify the spirit of innovation in the semiconductor field. His patent reflects a significant advancement that could influence future developments in integrated circuits.