Simpang Ampat, Malaysia

Chee Jong Loh

This inventor holds 1 USPTO granted patent. Top assignee: Lumileds Singapore Pte. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chee Jong Loh. Retrieved from https://idiyas.com/inventor/chee-jong-loh-m26ognp9

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chee Jong Loh: Semiconductor Invention and Patent

Introduction

Chee Jong Loh is an inventor associated with Simpang Ampat, Malaysia. His work includes a patented semiconductor structure and manufacturing methods, and he is associated with Lumileds Singapore Pte. Ltd.

Latest Patents

Loh is credited with 1 patent: “Semiconductor Structure and Methods of Manufacturing the Same.” The invention describes a semiconductor device electrically connected to a power source through an electrical contact and at least one bump. One example is an LED on a CMOS wafer, with the electrical contact positioned apart from the LED and placed on the wafer. Side-coating material surrounds the device and contact, while the bump or stacked bumps can extend to, or nearly to, the coating’s top surface. The coating may expose the top surface of the bump.

Career Highlights

The patent reflects Loh’s contribution to semiconductor packaging and electrical interconnection, particularly the arrangement of contacts, bumps, and side-coating material. He is associated with Lumileds Singapore Pte. Ltd.

Collaborations

Loh’s listed coworkers include Chee Teong Lim and Chee Ming Thoe. Their names are provided as professional associations, though the available information does not specify their roles in the patent.

Conclusion

Chee Jong Loh’s recorded patent focuses on a semiconductor structure designed to connect a device to a power source while integrating bumps and protective side coating.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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