Company Filing History:

12 out of 164,108

International Business Machines Corporation

Years Active: 2006-2020

where 'Filed Patents' based on already Granted Patents

13 patents (USPTO):Sort by Forward Citations

Abstract keywords

1. 10684861 - Enhanced performance-aware instruction scheduling (2020-06-16),

2. 10649781 - Enhanced performance-aware instruction scheduling (2020-05-12),

3. 10552167 - Clock-gating for multicycle instructions (2020-02-04),

4. 10324816 - Checking a computer processor design for soft error handling (2019-06-18),

5. 10318395 - Checking a computer processor design for soft error handling (2019-06-11),

6. 10275391 - Combining of several execution units to compute a single wide scalar result (2019-04-30),

7. 9977680 - Clock-gating for multicycle instructions (2018-05-22),

8. 9959093 - Binary fused multiply-add floating-point calculations (2018-05-01),

9. 9952829 - Binary fused multiply-add floating-point calculations (2018-04-24),

10. 9734126 - Post-silicon configurable instruction behavior based on input operands (2017-08-15),

11. 9297856 - Implementing MISR compression methods for test time reduction (2016-03-29),

12. 9274545 - Apparatus and method to recover a data signal (2016-03-01),

13. 6989696 - System and method for synchronizing divide-by counters (2006-01-24),

Title: Inventor Cédric Lichtenau: A Pioneer in Instruction Scheduling Innovations

Introduction

Cédric Lichtenau, an accomplished inventor located in Stuttgart, Germany, has made significant contributions to the field of computer processors with a total of 13 patents to his name. His work primarily focuses on enhancing performance in instruction scheduling, which plays a crucial role in optimizing the efficiency of modern processors.

Latest Patents

One of Lichtenau's latest innovations is titled "Enhanced Performance-Aware Instruction Scheduling." This patent relates to a method for instruction processing using a processor with multiple execution units. The processor features a dependency cache that stores instructions along with associated execution unit indicators. The method entails tracking the number of dependent instructions currently assigned to each execution unit. When a new instruction from a dependency chain is received, the execution unit linked to the prior instruction in the chain can be identified. If the identified execution unit has exceeded a predefined maximum number of dependent instructions, another execution unit will be selected for scheduling the new instruction. This innovative approach enhances overall processor performance, allowing for more efficient instruction processing.

Career Highlights

Throughout his career, Cédric Lichtenau has worked for notable companies, including International Business Machines Corporation (IBM) and GlobalFoundries Inc. His experience in these esteemed organizations has undoubtedly contributed to his expertise in processor technology and innovation.

Collaborations

Lichtenau has had the opportunity to collaborate with talented professionals in his field, including Nicol Hofmann and Michael Klein. Such collaborations have likely fostered a rich exchange of ideas and furthered advancements in instruction scheduling methodologies.

Conclusion

Cédric Lichtenau stands out as a prominent inventor in the realm of instruction scheduling innovations. His 13 patents, including the groundbreaking "Enhanced Performance-Aware Instruction Scheduling," reflect his commitment to improving processor efficiency. Through his career and collaborations, Lichtenau continues to make a lasting impact on the technological landscape.

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