The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Mar. 08, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Erez Barak, Kfar Saba, IL;

Nicol Hofmann, Stuttgart, DE;

Cédric Lichtenau, Stuttgart, DE;

Osher Yifrach, Modiin, IL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/26 (2006.01); G06F 17/50 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 11/261 (2013.01); G06F 11/3672 (2013.01); G06F 17/5009 (2013.01);
Abstract

Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.


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