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For the Inventor, By the Inventor

Palo Alto, CA, United States of America

Brian D Emberling

This inventor holds 55 USPTO granted patents and 8 published patent applications and 7 EPO patents, primarily in Graphics Processing. Top assignees: Advanced Micro Devices Corporation, Sun Microsystems, Inc., Ati Technologies Ulc. Active years: 2001-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Brian D Emberling. Retrieved from https://idiyas.com/inventor/brian-d-emberling

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 55 

% Patents Active = 98.2

 

Average Co-Inventor Count = 2.1

ph-index = 10

Forward Citations = 445(Granted Patents)

Forward Citations (Not Self Cited) = 436(Dec 10, 2025)


Location History:

  • San Francisco, CA (US) (2001)
  • San Mateo, CA (US) (2004 - 2017)
  • Sunnyvale, CA (US) (2018 - 2022)
  • Palo Alto, CA (US) (2012 - 2024)
  • Santa Clara, CA (US) (2022 - 2024)

Company Filing History:

goldMedal28 out of 13,185 
 
Advanced Micro Devices Corporation
 patents
silverMedal26 out of 7,642 
 
Sun Microsystems, Inc.
 patents
bronzeMedal2 out of 1,125 
 
Ati Technologies Ulc
 patents
4. 1 out of 1,928 
 
Oracle America, Inc.
 patents
where one patent can have more than one assignee

Years Active: 2001-2026

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Areas of Expertise:
SIMD Execution
Memory Optimization
Multi-Threading Techniques
Graphics Accelerators
Texture Mapping
Cache Structure
Instruction Scheduling
Data Prefetching
Thread Monitoring
Pipeline Stalling
Dynamic Control
Power Control
55 patents (USPTO):Explore Patents
1. 12646249 - System and method for executing a task (2026-06-02),
2. 12645751 - Convolutional neural network operations (2026-06-02),
3. 12645362 - Systems and methods for providing extended memory access in a parallel processor (2026-06-02),
4. 12517771 - Hardware supported split barrier (2026-01-06),
5. 12299413 - Dual vector arithmetic logic unit (2025-05-13),
6. 12229570 - Block data load with transpose into memory (2025-02-18),
7. 12033275 - System and methods for efficient execution of a collaborative task in a shader system (2024-07-09),
8. 12033238 - Register compaction with early release (2024-07-09),
9. 11880683 - Packed 16 bits instruction pipeline (2024-01-23),
10. 11847462 - Software-based instruction scoreboard for arithmetic logic units (2023-12-19),
11. 11675568 - Dual vector arithmetic logic unit (2023-06-13),
12. 11386518 - Exception handler for sampling draw dispatch identifiers (2022-07-12),
13. 11226819 - Selective prefetching in multithreaded processing units (2022-01-18),
14. 11074075 - Wait instruction for preventing execution of one or more instructions until a load counter or store counter reaches a specified value (2021-07-27),
15. 10474468 - Indicating instruction scheduling mode for processing wavefront portions (2019-11-12),

Title: The Inventor Brian D Emberling

Introduction: Brian D Emberling is a renowned inventor based in Palo Alto, California. He is known for his groundbreaking contributions to various fields through his innovative creations.

Latest Patents: Brian D Emberling holds several patents in the areas of technology, healthcare, and sustainable energy. His most recent patents focus on enhancing communication systems and improving medical devices.

Career Highlights: With a career spanning over two decades, Brian D Emberling has worked with leading tech companies and research institutions to develop cutting-edge solutions. His expertise lies in transforming ideas into practical inventions that have a positive impact on society.

Collaborations: Throughout his career, Brian D Emberling has collaborated with top engineers, scientists, and designers to bring his inventions to life. His collaborative approach has led to the successful implementation of complex projects.

Conclusion: Brian D Emberling's passion for innovation and his dedication to pushing the boundaries of technology make him a standout figure in the world of inventors. His relentless pursuit of excellence continues to inspire the next generation of innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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