Rousset, France

Bernard Cadet

This inventor holds 1 USPTO granted patent. Top assignee: Sgs-Thomson Microelectronics S.a.. Active years: 2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Bernard Cadet. Retrieved from https://idiyas.com/inventor/bernard-cadet-i62cu7yy

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.0

ph-index = 1

Forward Citations = 27(Granted Patents)


Company Filing History:


Years Active: 2003

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1 patent (USPTO):Explore Patents

Title: The Innovative Contributions of Bernard Cadet

Introduction

Bernard Cadet is a notable inventor based in Rousset, France. He has made significant contributions to the field of integrated circuits, particularly through his innovative methods for marking these circuits. His work has implications for the quality control processes in semiconductor manufacturing.

Latest Patents

Bernard Cadet holds a patent for a "Method for marking integrated circuits with a laser." This method involves physically marking silicon wafers of integrated circuits that are deemed defective during testing. The marking modifies the visual appearance of the surface of these circuits by exposing them to a laser beam. The patent also includes the disclosure of an instrument that enables the implementation of this method. He has 1 patent to his name.

Career Highlights

Bernard Cadet is associated with STMicroelectronics, a leading company in the semiconductor industry. His role at the company has allowed him to contribute to advancements in technology and innovation in integrated circuits. His expertise in laser marking techniques has enhanced the efficiency of identifying defective circuits.

Collaborations

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Conclusion

Bernard Cadet's innovative work in marking integrated circuits has made a significant impact on the semiconductor industry. His contributions continue to influence quality control processes and enhance the reliability of integrated circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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