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For the Inventor, By the Inventor

San Jose, CA, United States of America

Azalia Mirhoseini

This inventor holds 20 USPTO granted patents and 10 published patent applications and 4 EPO patents, primarily in Neural Network Optimization. Top assignee: Google Inc.. Active years: 2019-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Azalia Mirhoseini. Retrieved from https://idiyas.com/inventor/azalia-mirhoseini

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 20 

% Patents Active = 100.0

 

Average Co-Inventor Count = 6.8

ph-index = 2

Forward Citations = 19(Granted Patents)


Location History:

  • San Jose, CA (US) (2019 - 2023)
  • Mountain View, CA (US) (2023 - 2024)

Company Filing History:

goldMedal20 out of 33,959 
 
Google Inc.
 patents

Years Active: 2019-2026

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Areas of Expertise:
DNN Accelerators
Integrated Circuit Placement
Graph Optimizations
Neural Networks
Reinforcement Learning
Device Placement
Floorplanning
Approximate Computing
Hierarchical Placement
Mixture of Experts
20 patents (USPTO):Explore Patents
1. 12554675 - Synthesizing zero-loss low-power approximate DNN accelerators with large-scale search (2026-02-17),
2. 12488164 - Alignment cost for integrated circuit placement (2025-12-02),
3. 12461723 - Learned graph optimizations for compilers (2025-11-04),
4. 12248745 - Generating integrated circuit placements using neural networks (2025-03-11),
5. 12205038 - Computational graph optimization (2025-01-21),
6. 12086516 - Generating integrated circuit floorplans using neural networks (2024-09-10),
7. 12067476 - Mixture of experts neural networks (2024-08-20),
8. 11853677 - Generating integrated circuit placements using neural networks (2023-12-26),
9. 11803747 - Device placement optimization with reinforcement learning (2023-10-31),
10. 11790214 - Mixture of experts neural networks (2023-10-17),
11. 11675940 - Generating integrated circuit floorplans using neural networks (2023-06-13),
12. 11657289 - Computational graph optimization (2023-05-23),
13. 11556690 - Generating integrated circuit placements using neural networks (2023-01-17),
14. 11455514 - Hierarchical device placement with reinforcement learning (2022-09-27),
15. 11216609 - Generating integrated circuit placements using neural networks (2022-01-04),

Title: The Innovative Work of Inventor Azalia Mirhoseini

Introduction

Azalia Mirhoseini, a prolific inventor based in San Jose, CA, has made significant contributions to the field of technology with her inventive spirit and forward-thinking approach.

Latest Patents

Mirhoseini's latest patents include "Generating integrated circuit placements using neural networks" and "Device placement optimization with reinforcement learning." These patents demonstrate her expertise in creating cutting-edge solutions for computer chip placements and machine learning model operations across multiple hardware devices.

Career Highlights

With a notable portfolio of 13 patents under her belt, Azalia Mirhoseini has established herself as a trailblazer in the tech industry. Her innovative techniques have paved the way for advancements in the areas of integrated circuit placements and device placement optimization.

Collaborations

Mirhoseini's work at Google Inc. has allowed her to collaborate with esteemed colleagues such as Jeffrey Adgate Dean and Anna Darling Goldie. Together, they have spearheaded projects that have revolutionized the way technology is integrated and optimized for enhanced performance.

Conclusion

In conclusion, Azalia Mirhoseini's inventive prowess and dedication to pushing the boundaries of technology have positioned her as a leading figure in the world of innovation. Her patents stand as a testament to her remarkable achievements and ongoing commitment to driving progress in the tech industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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