This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Baya Systems, Inc.. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: Avinash Jagdish Patil: Innovator in Network on Chip Technology
Introduction
Avinash Jagdish Patil is an inventor based in Bengaluru, India. He has made significant contributions to the field of Network on Chip (NoC) technology. His innovative approach focuses on enhancing communication efficiency within NoC systems.
Latest Patent Applications
Avinash has filed a patent application titled "IN-LINK FLIT RESIZING WITH END-TO-END CREDITS." This application describes systems and methods involving a wide-to-narrow in-link converter for NoC. The converter processes wide flits from the source router, transforming them into multiple narrow flits efficiently popped to the destination router. A link credit is returned to the source router post-transfer. The converter also handles diverse wide flit types, converting and popping them accordingly. Additionally, a narrow-to-wide converter accumulates and converts narrow flits into wide flits, optimizing communication efficiency in the NoC and overcoming traditional limitations.
Conclusion
Avinash Jagdish Patil is an emerging inventor whose work in NoC technology promises to enhance communication systems significantly. His innovative patent application reflects his commitment to advancing this field.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile