Atul Bhagat

Title: Atul Bhagat and Automated Clock-Relationship Management

Introduction

Atul Bhagat is an inventor based in San Jose, California, whose patent work addresses the analysis and management of clock relationships in integrated circuit designs. His work is associated with Ausdia, Inc.

Latest Patents

Bhagat is named on 1 patent, titled “System and Method for Automatically Managing Clock Relationships in Integrated Circuit Designs.” The invention describes a computer-implemented method for analyzing clock-to-clock logical relationships in a proposed integrated circuit design. It can receive a design description, clock waveforms, and timing constraints, then identify relationships between clocks and classify them into behavioral categories. The resulting analysis can help verify existing timing exceptions or identify missing exceptions between clock pairs.

Career Highlights

The patent reflects work on automating a complex part of integrated circuit design verification. By organizing clock relationships into behavioral categories, the system aims to support more systematic review of timing constraints and exceptions.

Collaborations

Bhagat’s listed coworkers include Timothy P. Moore and Samuel S. Appleton. His patent is associated with Ausdia, Inc.

Conclusion

Atul Bhagat’s patented work focuses on automatically identifying and managing clock relationships to support timing analysis in integrated circuit designs.