Higashiosaka, Japan

Atsushi Yasunaka

This inventor holds 3 USPTO granted patents. Top assignees: Socionext Inc., Fujitsu Semiconductor Limited. Active years: 2013-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Atsushi Yasunaka. Retrieved from https://idiyas.com/inventor/atsushi-yasunaka

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 33.3

Average Co-Inventor Count = 1.2

ph-index = 2

Forward Citations = 6(Granted Patents)


Location History:

  • Higashiosaka, JP (2013 - 2016)
  • Yokohama, JP (2020)

Company Filing History:


Years Active: 2013-2020

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3 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Atsushi Yasunaka

Introduction

Atsushi Yasunaka is a notable inventor based in Higashiosaka, Japan. He has made significant contributions to the field of circuit design and high-level synthesis processes. With a total of 3 patents to his name, Yasunaka's work has had a considerable impact on semiconductor technology.

Latest Patents

Yasunaka's latest patents include a method, design program, and design apparatus for a high-level synthesis process of a circuit. This design method encompasses generating a hardware description of a circuit and high-level synthesis report information from a source code based on high-level synthesis constraints. The hardware description details a circuit with multiple stages and inter-stage registers. Additionally, it involves determining a bypass stage selection pattern based on bypass constraint information, which includes conditions related to bypassing inter-stage registers. Furthermore, the method generates bypass report information that includes combination details of the inter-stage registers for which bypass settings are applied according to predetermined priority conditions.

Another significant patent involves a high-level synthesis data generation apparatus, which analyzes a source code representing design data of a semiconductor device. This apparatus generates information indicating the data and control flow of the semiconductor device. The high-level synthesis data generation unit acquires intermediate data from the compiled source code and incorporates the generated control flow information into the acquired data, ultimately outputting it as high-level synthesis data.

Career Highlights

Throughout his career, Atsushi Yasunaka has worked with prominent companies in the semiconductor industry, including Socionext Inc. and Fujitsu Semiconductor Limited. His experience in these organizations has allowed him to refine his skills and contribute to innovative projects in circuit design.

Collaborations

Yasunaka has collaborated with various professionals in his field, including Kimitoshi Niratsuka. These collaborations have further enhanced his work and contributed to the development of advanced technologies.

Conclusion

Atsushi Yasunaka's innovative contributions to circuit design and high-level synthesis processes have established him as a significant figure in the semiconductor industry. His patents reflect his expertise and commitment to advancing technology in this field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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