Company Filing History:
Years Active: 2014
Title: Ashima Dabare: Innovator in Integrated Circuit Design
Introduction
Ashima Dabare is a prominent inventor based in Noida, India. She has made significant contributions to the field of integrated circuit design, particularly in the area of physical implementation analysis. Her innovative approach addresses critical challenges faced in the design process, enhancing the efficiency and reliability of integrated circuits.
Latest Patents
Ashima holds a patent for an "Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis." This invention provides a method for detecting physical implementation hot-spots in a pre-placement integrated circuit design. The method first identifies physical issues at an object level, which include timing, routing congestion, clocking, scan, power, and thermal concerns. It then analyzes these physical issues over a collection of connected logic cell and large cell instances, determining the severity of physical implementation hot-spots based on the number and severity of physical issues, as well as the number of objects in the related collection. She has 1 patent to her name.
Career Highlights
Ashima is currently employed at Atrenta, Inc., where she continues to develop innovative solutions for integrated circuit design challenges. Her work has been instrumental in advancing the methodologies used in the industry, making her a valuable asset to her team and the broader engineering community.
Collaborations
Throughout her career, Ashima has collaborated with talented professionals, including Jitendra Kumar Gupta and Kshitiz Krishna. These collaborations have fostered a creative environment that encourages innovation and problem-solving.
Conclusion
Ashima Dabare's contributions to integrated circuit design exemplify the impact of innovative thinking in technology. Her patent and ongoing work at Atrenta, Inc. highlight her commitment to advancing the field and addressing complex challenges in circuit design.