Crolles, France

Arnaud Lepert

This inventor holds 1 USPTO granted patent. Top assignee: Sgs-Thomson Microelectronics S.a.. Active years: 2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Arnaud Lepert. Retrieved from https://idiyas.com/inventor/arnaud-lepert-uky6ur0a

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2003

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1 patent (USPTO):Explore Patents

Title: Arnaud Lepert: Innovator in Silicon Layer Doping Techniques

Introduction

Arnaud Lepert is a notable inventor based in Crolles, France. He has made significant contributions to the field of semiconductor technology, particularly in the modification of silicon layers. His innovative approach has implications for various electronic applications.

Latest Patents

Lepert holds a patent for a method aimed at modifying the doping level of a silicon layer. This method involves coating the silicon layer with a silicide layer made of a refractory metal and heating the interface region between the silicon and the silicide to a predetermined temperature. This technique can be applied in the fabrication of adjustable resistors or MOS transistors with adjustable thresholds. He has 1 patent to his name.

Career Highlights

Arnaud Lepert is associated with STMicroelectronics, a leading company in the semiconductor industry. His work focuses on enhancing the performance and versatility of silicon-based devices, contributing to advancements in electronic components.

Collaborations

Lepert collaborates with Alexander Kalnitsky, working together to push the boundaries of semiconductor technology and innovate new solutions in their field.

Conclusion

Arnaud Lepert's contributions to the modification of silicon layers exemplify the importance of innovation in the semiconductor industry. His work continues to influence the development of advanced electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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