Seongnam, South Korea

Anthony Payet

This inventor holds 1 USPTO granted patent. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Anthony Payet. Retrieved from https://idiyas.com/inventor/anthony-payet

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 8.0

ph-index = 1


Company Filing History:


Years Active: 2021

Loading Chart...
1 patent (USPTO):Explore Patents

Title: The Innovative Mind of Anthony Payet

Introduction

Anthony Payet is a notable inventor based in Seongnam-si, South Korea. He has made significant contributions to the field of semiconductor technology. His work focuses on simulation methods that enhance the design and efficiency of semiconductor chips.

Latest Patents

Anthony Payet holds a patent for a "Simulation method and system." This innovative method involves storing a variety of structure parameters of transistors for a semiconductor chip. It includes generating local layouts that incorporate actual parameters determined through imaging equipment. The method further modifies these parameters to calculate effective density factors and epitaxy times, ultimately improving chip design.

Career Highlights

Payet is currently employed at Samsung Electronics Co., Ltd., a leading company in the technology sector. His role involves applying his expertise in semiconductor design and simulation. He has been instrumental in advancing the company's capabilities in this competitive field.

Collaborations

Throughout his career, Anthony has collaborated with talented individuals such as Alexander Schmidt and Dong-Gwan Shin. These partnerships have fostered innovation and contributed to the success of various projects.

Conclusion

Anthony Payet's contributions to semiconductor technology through his innovative simulation methods highlight his importance in the field. His work continues to influence advancements in chip design and efficiency.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…