Beijing, China

Anlan Chen

This inventor holds 1 USPTO granted patent. Top assignee: Chinese Academy of Sciences. Active years: 2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Anlan Chen. Retrieved from https://idiyas.com/inventor/anlan-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 7.0

ph-index = 1


Company Filing History:


Years Active: 2025

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1 patent (USPTO):Explore Patents

Title: Anlan Chen and Semiconductor Device Innovation.

Introduction

Anlan Chen is an inventor based in Beijing, China. His patent work concerns semiconductor device design and manufacturing, including gate-all-around transistor structures.

Latest Patents

Chen is associated with 1 patent: “Semiconductor Device and Method for Manufacturing the Same.” The invention describes a semiconductor device with first and second gate-all-around (GAA) transistors in separate regions. The first transistor includes one or more nanowire or nanosheet layers, while the second includes at least two such layers. The design specifies that the minimum spacing between adjacent layers in the first group is greater than the maximum spacing in the second group, and that the first group has fewer layers. The patent also addresses a method for manufacturing the device.

Career Highlights

Chen is associated with the Chinese Academy of Sciences. His listed patent reflects work on nanoscale transistor architecture and semiconductor manufacturing.

Collaborations

Fei Zhao and Yongliang Li are listed as Chen’s coworkers. Their shared institutional association provides context for his professional network.

Conclusion

Anlan Chen’s patent focuses on differentiated layer spacing and layer counts in GAA transistors, contributing to innovation in semiconductor device design and manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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