This inventor holds 2 USPTO granted patents. Top assignee: Cisco Technology, Inc.. Active years: 2013-2014.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2013-2014
Title: Andrew V Kearney: Innovator in Semiconductor Technology
Introduction
Andrew V Kearney is a notable inventor based in Santa Clara, CA (US). He has made significant contributions to the field of semiconductor technology, holding a total of 2 patents. His work focuses on improving the reliability and efficiency of semiconductor packages.
Latest Patents
Kearney's latest patents include a method of fabricating a semiconductor package with an integrated substrate thermal slug. This innovation aims to reduce thermal stresses that may arise from differences in thermal expansion coefficients between a molded casing and the active side of a semiconductor device. By arranging the active side of the semiconductor device face-down towards a substrate, Kearney's design minimizes failures caused by thermal stresses. The semiconductor device features a through via that electrically connects the active side to the passive side, with a wire bond linking the passive side to the substrate. Additionally, to enhance heat dissipation, a thermally conductive slug can be integrated into the substrate, allowing the active side of the semiconductor device to be attached to it.
Career Highlights
Andrew V Kearney is currently employed at Cisco Technology, Inc., where he continues to innovate in the semiconductor field. His expertise and contributions have positioned him as a valuable asset to the company.
Collaborations
Kearney collaborates with Peng Su, further enhancing the innovative efforts within their team.
Conclusion
Andrew V Kearney's work in semiconductor technology exemplifies the importance of innovation in enhancing device reliability and performance. His patents reflect a commitment to advancing the field and addressing critical challenges in semiconductor design.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
