Sacramento, CA, United States of America

Andrew Shu

This inventor holds 2 USPTO granted patents and 4 published patent applications. Top assignee: Permiso Security Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Andrew Shu. Retrieved from https://idiyas.com/inventor/andrew-shu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

% Patents Active = 50.0

Average Co-Inventor Count = 11.0

ph-index = 1


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Innovations by Andrew Shu in Integrated Circuit Structures

Introduction

Andrew Shu is an inventor based in Hillsboro, OR (US). He has made significant contributions to the field of integrated circuit structures. His innovative approach focuses on enhancing the architecture of transistors, which is crucial for the advancement of electronic devices.

Latest Patent Applications

Andrew Shu has filed a patent application titled "INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TRENCH CONTACT CUT IN A FORKSHEET TRANSISTOR ARCHITECTURE." This application describes integrated circuit structures that feature a dielectric backbone. The design includes first and second vertical stacks of nanowires that are laterally adjacent to and in contact with the first and second sides of the dielectric backbone. Additionally, first and second gate electrodes surround the vertical stacks of nanowires and are in contact with the dielectric backbone. The application also details a first dielectric cut plug structure adjacent to the first gate electrode and a second dielectric cut plug structure adjacent to the second gate electrode, with both structures being parallel to each other.

Conclusion

Andrew Shu's work in integrated circuit structures showcases his innovative spirit and dedication to advancing technology in the field of electronics. His patent application reflects a promising direction for future developments in transistor architecture.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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