Essex, VT, United States of America

Andres G Fortino

This inventor holds 2 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 1981-1983.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Andres G Fortino. Retrieved from https://idiyas.com/inventor/andres-g-fortino

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.4

ph-index = 2

Forward Citations = 54(Granted Patents)


Location History:

  • Essex, VT (US) (1981)
  • Bryn Mawr, PA (US) (1983)

Company Filing History:


Years Active: 1981-1983

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2 patents (USPTO):Explore Patents

Title: **Innovative Contributions of Inventor Andres G Fortino**

Introduction

Andres G Fortino, a distinguished inventor located in Essex, Vermont, has made significant contributions to the field of semiconductor technology. With two patents to his name, his innovations reflect a deep understanding of the intricacies involved in the development of IGFET devices and transistor arrays. Fortino currently works at the International Business Machines Corporation, commonly known as IBM, where he continues to shape the future of technology.

Latest Patents

Fortino's latest patents encompass groundbreaking methods that address key challenges in semiconductor manufacturing. The first patent, titled "Method for forming IGFET devices having improved drain voltage," describes a technique for creating less than one-micron p-n junction regions. By implanting a high concentration of arsenic near the surface of a semiconductor substrate, he achieves improved performance in these devices. Additionally, a second impurity, phosphorus, is introduced in a manner designed to optimize the concentration levels necessary for efficient operation.

The second patent, "Method of making a transistor array," outlines an innovative approach to forming transistor arrays. This method includes the formation of gate electrodes insulated from a semiconductor substrate, which contains impurities of varying conductivities. The introduction of arsenic and boron impurities facilitates the creation of a high-threshold region under selected gate electrodes, enabling the production of read-only memory (ROM) capabilities. The careful control of impurity diffusivity is a hallmark of Fortino's inventive process, significantly enhancing the functionality of these semiconductor devices.

Career Highlights

Throughout his career at IBM, Fortino has demonstrated a commitment to innovation and excellence. His technical prowess in the realms of semiconductor fabrication and device design has positioned him as a valuable asset in technological advancements. The impact of his patents is evident in the way they push the boundaries of what's possible in integrated circuit technology.

Collaborations

Fortino's work has been enriched by collaborations with notable colleagues such as Henry J Geipel, Jr and Paul E Bakeman, Jr. These partnerships have fostered an environment of creativity and ingenuity, allowing them to tackle complex challenges and develop innovative solutions together.

Conclusion

Andres G Fortino's contributions to semiconductor technology exemplify the spirit of innovation that drives progress in the field. His patents not only reflect his expertise but also serve as a foundation for future advancements in IGFET devices and transistor arrays. As he continues his journey at IBM, Fortino remains a pivotal figure in the ongoing quest for technological excellence.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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